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Structured in Space, Randomized in Time: Leveraging Dropout in RNNs for Efficient Training.

, , , , , and . NeurIPS, page 24545-24555. (2021)

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Using Task Recomputation During Application Mapping in Parallel Embedded Architectures., , and . CDES, page 29-35. CSREA Press, (2006)Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors., , , and . SoCC, page 77-78. IEEE, (2006)Instruction Scheduling for Low Power., , , , and . VLSI Signal Processing, 37 (1): 129-149 (2004)Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations., , , , and . Ultra Low-Power Electronics and Design, Kluwer / Springer, (2004)Compilation for Distributed Memory Architectures., and . The Compiler Design Handbook, CRC Press, (2002)FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Adaptive prefetching for shared cache based chip multiprocessors., , and . DATE, page 773-778. IEEE, (2009)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)Memory bank aware dynamic loop scheduling., , , and . DATE, page 1671-1676. EDA Consortium, San Jose, CA, USA, (2007)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)