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Certified Timing Verification and the Transition Delay of a Logic Circuit.

, , , and . DAC, page 549-555. IEEE Computer Society Press, (1992)

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Multi-level Logic Simplification Using Don't Cares and Filters., , , and . DAC, page 277-282. ACM Press, (1989)Certified timing verification and the transition delay of a logic circuit., , , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (3): 333-342 (1994)Computation of floating mode delay in combinational circuits: practice and implementation., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1924-1936 (1993)Verification of asynchronous interface circuits with bounded wire delays., , , and . ICCAD, page 188-195. IEEE Computer Society / ACM, (1992)Multi-level logic minimization using implicit don't cares., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (6): 723-740 (1988)Code Optimization Techniques in Embedded DSP Microprocessors., , , , and . Des. Autom. Embed. Syst., 3 (1): 59-73 (1998)Certified Timing Verification and the Transition Delay of a Logic Circuit., , , and . DAC, page 549-555. IEEE Computer Society Press, (1992)Code Optimization Techniques for Embedded DSP Microprocessors., , , , and . DAC, page 599-604. ACM Press, (1995)Storage Assignment to Decrease Code Size., , , , and . ACM Trans. Program. Lang. Syst., 18 (3): 235-253 (1996)Storage Assignment to Decrease Code Size., , , , and . PLDI, page 186-195. ACM, (1995)