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Disambiguation of "Lee, Sung-Tae"

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Design of Algorithm for the 3D Object Representation Based on the Web3D Using X3D.

, , , , and . PDCAT, volume 3320 of Lecture Notes in Computer Science, page 98-105. Springer, (2004)

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Sung Lee

Tae-Gyu Sung

Tae-soo Lee

Tae-Hoon Lee

Heun Tae Lee

 

Other publications of authors with the same name

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 47 (4): 981-989 (2012)A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology., , , , , , , , , and 27 other author(s). ISSCC, page 430-432. IEEE, (2012)Design of Algorithm for the 3D Object Representation Based on the Web3D Using X3D., , , , and . PDCAT, volume 3320 of Lecture Notes in Computer Science, page 98-105. Springer, (2004)A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 56 (4): 1129-1140 (2021)NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)., , , , and . IEEE Access, (2020)Low-Power Binary Neuron Circuit With Adjustable Threshold for Binary Neural Networks Using NAND Flash Memory., , and . IEEE Access, (2020)Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks., , , , and . Neurocomputing, (2022)A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems., , , , , , , , , and 16 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)