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spiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System.

, , , , , , , и . IEEE Access, (2020)

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Jamie Garside

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Jim Wilenius

Jim Kallarackal

Jim Tsen

 

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The Amulet chips: Architectural development for asynchronous microprocessors., , , и . ICECS, стр. 343-346. IEEE, (2009)AMULET1: A Micropipelined ARM., , , , и . COMPCON, стр. 476-485. IEEE Computer Society, (1994)An asynchronous copy-back cache architecture., , и . Microprocess. Microsystems, 27 (10): 485-500 (2003)Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application., , , , и . IEEE Trans. Biomed. Circuits Syst., 12 (5): 1018-1026 (2018)Analysis of software and hardware-accelerated approaches to the simulation of unconventional interconnection networks., , , , , и . Simul. Model. Pract. Theory, (2020)An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults., , , , и . ASYNC, стр. 9-16. IEEE Computer Society, (2014)AMULET3i Cache Architecture., и . ASYNC, стр. 152-161. IEEE Computer Society, (2001)Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA., , , и . DSD, стр. 607-614. IEEE Computer Society, (2014)An Asynchronous Victim Cache., , и . DSD, стр. 4-11. IEEE Computer Society, (2002)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , и 9 other автор(ы). ISCAS, стр. 1-4. IEEE, (2017)