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Disambiguation of "Fang, Zhenman"

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SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.

, , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 28:1-28:33 (June 2023)

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Fang-Fang Tang

Xianjie Fang

Jie Fang

Fang Cao

Fang Huang

 

Other publications of authors with the same name

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms., , , , , and . DAC, page 109:1-109:6. ACM, (2016)ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only)., , , and . FPGA, page 281. ACM, (2016)FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization., , , , , , , and . FPGA, page 134-145. ACM, (2022)SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs., , and . FPL, page 286-293. IEEE, (2021)Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking., , , , , , and . ACM Trans. Archit. Code Optim., 11 (4): 55:1-55:26 (2014)Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications., , , and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 29:1-29:2 (2022)Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks., , , , , and . ICFPT, page 3-4. IEEE, (2023)HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks., , , , , and . FCCM, page 203. IEEE, (2023)High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms., , , , , and . FCCM, page 37-44. IEEE Computer Society, (2018)Hardware-efficient stochastic rounding unit design for DNN training: late breaking results., , , , , , , , , and 2 other author(s). DAC, page 1396-1397. ACM, (2022)