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Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.

, , and . DFT, page 31-40. IEEE Computer Society, (2007)

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A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocks., , , and . DDECS, page 305-308. IEEE Computer Society, (2010)Testing approach within FPGA-based fault tolerant systems., and . Asian Test Symposium, page 411-416. IEEE Computer Society, (2000)Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems., , and . DSD, page 231-238. IEEE Computer Society, (2011)Defect and Fault Tolerance FPGAs by Shifting the Configuration Data., , and . DFT, page 377-385. IEEE Computer Society, (1999)Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift., , and . IOLTS, page 203-204. IEEE Computer Society, (2005)Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources., and . DFT, page 134-142. IEEE Computer Society, (2000)Testing the Logic Cells and Interconnect Resources for FPGAs., and . Asian Test Symposium, page 369-374. IEEE Computer Society, (1999)Video acquisition between USB 2.0 CMOS camera and embedded FPGA system., , , , , , and . ICSPCS, page 1-5. IEEE, (2011)Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey., and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 386-405 (2003)Fault tolerance of SRAM-based FPGA via configuration frames., , and . DDECS, page 139-142. IEEE Computer Society, (2011)