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Disambiguation of "Shanbhag, Naresh R."

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Generalized Water-filling for Source-Aware Energy-Efficient SRAMs.

, , , and . CoRR, (2017)

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Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Other publications of authors with the same name

A low-power bus design using joint repeater insertion and coding., and . ISLPED, page 99-102. ACM, (2005)Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers., and . ISLPED, page 334-339. ACM, (2001)An In-Memory VLSI Architecture for Convolutional Neural Networks., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 494-505 (2018)Analytical Guarantees on Numerical Precision of Deep Neural Networks., , and . ICML, volume 70 of Proceedings of Machine Learning Research, page 3007-3016. PMLR, (2017)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , and . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Analytical estimation of signal transition activity from word-level statistics., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)A Study of BER-Optimal ADC-Based Receiver for Serial Links., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 693-704 (2016)Linear turbo equalization analysis via BER transfer and EXIT charts., , and . IEEE Trans. Signal Process., 53 (8-1): 2883-2897 (2005)Signal Processing for High-Speed Links., , and . Handbook of Signal Processing Systems, Springer, (2013)Area-efficient high-throughput MAP decoder architectures., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)