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Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL., , and . Algorithms, 12 (8): 149 (2019)Cache Remapping to Improve the Performance of Tiled Algorithms., and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 998-1007. Springer, (2000)Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler., , , and . DELTA, page 142-147. IEEE Computer Society, (2008)Comparing and combining GPU and FPGA accelerators in an image processing context., , , , , and . FPL, page 1-4. IEEE, (2013)Performance Modeling of Microkernel Thread Schedulers for Shared Memory Multiprocessors., , and . PARLE, volume 694 of Lecture Notes in Computer Science, page 736-739. Springer, (1993)Visualization Enables the Programmer to Reduce Cache Misses., , and . IASTED PDCS, page 774-781. IASTED/ACTA Press, (2002)ParaFPGA 2017: Enlarging the Scope of Parallel Programming with FPGAs., and . PARCO, volume 32 of Advances in Parallel Computing, page 619-621. IOS Press, (2017)Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse., and . International Conference on Computational Science, volume 3038 of Lecture Notes in Computer Science, page 448-455. Springer, (2004)Compiler Generated Multithreading to Alleviate Memory Latency., and . J. Univers. Comput. Sci., 6 (10): 968-993 (2000)ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications., , and . PARCO, volume 25 of Advances in Parallel Computing, page 493-496. IOS Press, (2013)