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Factory Environment Monitoring: A Japanese Tea Manufacturer's Case.

, и . ICCE, стр. 1-3. IEEE, (2019)

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Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

 

Другие публикации лиц с тем же именем

Delay Testing: Improving Test Quality and Avoiding Over-testing., , и . IPSJ Trans. Syst. LSI Des. Methodol., (2011)A Method of Diagnostic Test Generation for Transition Faults., и . PRDC, стр. 273-278. IEEE Computer Society, (2015)A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency., , , и . Asian Test Symposium, стр. 306-311. IEEE Computer Society, (2005)Design for Testability Based on Single-Port-Change Delay Testing for Data Paths., , , и . Asian Test Symposium, стр. 254-259. IEEE Computer Society, (2005)A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification., , , и . VTS, стр. 71-76. IEEE Computer Society, (2009)Factory Environment Monitoring: A Japanese Tea Manufacturer's Case., и . ICCE, стр. 1-3. IEEE, (2019)Fast false path identification based on functional unsensitizability using RTL information., , , и . ASP-DAC, стр. 660-665. IEEE, (2009)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , и . VLSI-SoC (Selected Papers), том 249 из IFIP, стр. 301-316. Springer, (2006)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , и . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , и . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)