( en | de | ru )

 

Disambiguation of "Sarbazi-Azad, Hamid"

Author of the publication

copydeleteadd this publication to your clipboard
Evaluation of Hardware Data Prefetchers on Server Processors.

, , , and . ACM Comput. Surv., 52 (3): 52:1-52:29 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ataollah Azadi-Bakhsh

Mohsen Azadbakht

Esfandyar Azadi-Rad

Hassan Azadeh

Behnam Azadegan

 

Other publications of authors with the same name

An efficient DVS scheme for on-chip networks using reconfigurable Virtual Channel allocators., , , and . ISLPED, page 249-254. IEEE, (2015)High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement., , and . ISLPED, page 79-84. IEEE/ACM, (2011)Comparative Evaluation of Adaptive and Deterministic Routing in the OTIS-Hypercube., and . Asia-Pacific Computer Systems Architecture Conference, volume 3189 of Lecture Notes in Computer Science, page 349-362. Springer, (2004)Power-efficient partially-adaptive routing in on-chip mesh networks., , and . ISOCC, page 65-66. IEEE, (2016)Design for scalability in enterprise SSDs., , and . PACT, page 417-430. ACM, (2014)An Analytic Model for Communication Latency in Wormhole-Switched k-ary n-Cube Interconnection Networks with Digit-Reversal Traffic., , and . ISHPC, volume 1940 of Lecture Notes in Computer Science, page 218-229. Springer, (2000)A Parallel Algorithm for Lagrange Interpolation on k-ary n-Cubes., , and . ACPC, volume 1557 of Lecture Notes in Computer Science, page 85-95. Springer, (1999)Traffic-aware buffer reconfiguration in on-chip networks., and . VLSI-SoC, page 201-206. IEEE, (2015)Advances in multicore systems architectures., , and . J. Supercomput., 71 (8): 2783-2786 (2015)An accurate performance model of fully adaptive routing in wormhole-switched two-dimensional mesh multicomputers., , and . Microprocess. Microsystems, 31 (7): 445-455 (2007)