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Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.

, , , , , and . PATMOS, page 111-117. IEEE, (2015)

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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs., , , and . IOLTS, page 187-192. IEEE Computer Society, (2004)Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor., , , , , and . PATMOS, page 111-117. IEEE, (2015)On the Reliability Evaluation of SRAM-Based FPGA Designs., , and . FPL, page 403-408. IEEE, (2005)Requirements for delay testing of look-up tables in SRAM-based FPGAs., , , and . ETW, page 147-152. IEEE Computer Society, (2003)Impact of power management on temperature and reliability evolution for an embedded many-core architecture., , , and . ARCS Workshops, VDE-Verlag, (2011)Identifying aging-aware representative paths in processors., and . IOLTS, page 32-33. IEEE, (2015)Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs., , , and . J. Electron. Test., 21 (1): 43-55 (2005)High Quality TPG for Delay Faults in Look-Up Tables of FPGAs., , , and . DELTA, page 83-88. IEEE Computer Society, (2004)Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs., , , and . ETS, page 52-57. IEEE Computer Society, (2004)When processors get old: Evaluation of BTI and HCI effects on performance and reliability., , , and . IOLTS, page 185-186. IEEE, (2013)