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Disambiguation of "Su, Pin"

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Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS.

, , , , , , and . CICC, page 381-384. IEEE, (2001)

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Pin Nie

Salomon Pin

Chia-Pin Chang

Pin-Chia Lee

Chang-Pin Lin

 

Other publications of authors with the same name

Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , and . ISCAS, page 1122-1125. IEEE, (2014)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , and . ESSDERC, page 77-80. IEEE, (2012)Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells., , and . ISLPED, page 242-247. ACM, (2016)Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM., , , , and . APCCAS, page 471-474. IEEE, (2012)Design and analysis of ultra-thin-body SOI based subthreshold SRAM., , , , and . ISLPED, page 9-14. ACM, (2009)Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling., , , , and . ISCAS, page 1130-1133. IEEE, (2014)Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 335-342 (2011)Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications., , , , , and . SoCC, page 339-344. IEEE, (2015)Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1201-1210 (2012)Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling., , , and . ICICDT, page 1-4. IEEE, (2016)