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Partial access conflict-relieving programmable address shuffler for parallel memory system in multi-core processor., и . Microprocess. Microsystems, 34 (1): 1-13 (2010)Functional Coverage Metric Generation from Temporal Event Relation Graph., и . DATE, стр. 670-671. IEEE Computer Society, (2004)MDSP-II: 16-bit DSP with mobile communication accelerator., , , , , , , и . CICC, стр. 5-8. IEEE, (1998)A 159.2mW SoC implementation of T-DMB receiver including stacked memories., , , , , , , , , и . CICC, стр. 679-682. IEEE, (2008)Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor., , и . FPL, стр. 209-214. IEEE, (2008)Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor., , и . ASP-DAC, стр. 329-334. IEEE, (2009)FLOVA: A four-issue VLIW geometry processor with SIMD instructions and lighting acceleration unit., , , , , , , , и . CICC, стр. 551-554. IEEE, (2000)DIVA: dual-issue VLIW architecture with media instructions for image processing., , , , и . IEEE Trans. Consumer Electronics, 45 (1): 192-202 (1999)Systematic functional coverage metric synthesis from hierarchical temporal event relation graph., , и . DAC, стр. 45-48. ACM, (2004)MetaCore: An Application Specific DSP Development System., , , , , , , , , и 12 other автор(ы). DAC, стр. 800-803. ACM Press, (1998)