( en | de | ru )

 

Disambiguation of "Cheng, Chung-Kuan"

Author of the publication

copydeleteadd this publication to your clipboard
Evaluating a bounded slice-line grid assignment in O(nlogn) time.

, , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chung-hsin Cheng

Yuan-Chung Cheng

Wen Chung Cheng

Chung-tao Cheng

Cheng Han Chung

 

Other publications of authors with the same name

Floorplanning with abutment constraints based on corner block list., , , , , and . Integr., 31 (1): 65-77 (2001)On general zero-skew clock net construction., and . IEEE Trans. Very Large Scale Integr. Syst., 3 (1): 141-146 (1995)Routability improvement using dynamic interconnect architecture., and . IEEE Trans. Very Large Scale Integr. Syst., 6 (3): 498-501 (1998)Corner block list representation and its application to floorplan optimization., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 51-II (5): 228-233 (2004)Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs., , , , , , , and . Networks, 76 (1): 106-121 (2020)Optimization by iterative improvement: an experimental evaluation on two-way partitioning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (2): 145-153 (1995)Symbolic layout compaction under conditional design rules., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (4): 475-486 (1992)Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 645-658 (2007)Sequence-pair approach for rectilinear module placement., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (4): 484-493 (1999)A general purpose, multiple-way partitioning algorithm., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1480-1488 (1994)