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Disambiguation of "Jeon, Dongsuk"

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A 40nm 4.81TFLOPS/W 8b Floating-Point Training Processor for Non-Sparse Neural Networks Using Shared Exponent Bias and 24-Way Fused Multiply-Add Tree.

, , and . ISSCC, page 148-150. IEEE, (2021)

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Seonghye Jeon

Jinseong Jeon

Nadja Jeon

Donghwan Jeon

Jeongho Jeon

 

Other publications of authors with the same name

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector., , , , , and . IEEE J. Solid State Circuits, 53 (1): 50-65 (2018)A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS., , , , , , , and . IEEE J. Solid State Circuits, 52 (6): 1628-1642 (2017)A 65 nm 12.92-nJ/Inference Mixed-Signal Neuromorphic Processor for Image Classification., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (8): 2804-2808 (August 2023)Circuit techniques for miniaturized biomedical sensors., , , , , , , , , and 5 other author(s). CICC, page 1-7. IEEE, (2014)A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training., , and . ESSCIRC, page 145-148. IEEE, (2022)A low-power VGA full-frame feature extraction processor., , , , , and . ICASSP, page 2726-2730. IEEE, (2013)Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS., , , , and . APCCAS, page 734-735. IEEE, (2016)8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment., , , , , and . ISSCC, page 148-149. IEEE, (2017)Design techniques for ultra-efficient computing.. ISOCC, page 87-88. IEEE, (2016)Enhancing Reliability of Analog Neural Network Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1455-1459 (2019)