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Disambiguation of "Hsiao, Shen-Fu"

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Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling.

, , , and . ISCAS, page 608-611. IEEE, (2012)

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Chi-Yuan Hsiao

Lojen Hsiao

Kaijen Hsiao

Michael Kai Mikai Hsiao

He-Hsuan Hsiao

 

Other publications of authors with the same name

Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms., and . ASAP, page 324-335. IEEE, (1994)VLSI implementation of belief-propagation-based stereo matching with linear-model message update., , and . APCCAS, page 73-76. IEEE, (2014)Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction., , and . ISCAS, page 2022-2025. IEEE, (2008)Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (5): 287-291 (2013)Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (5): 466-470 (2015)Para-CORDIC: parallel CORDIC rotation algorithm., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (8): 1515-1524 (2004)A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array., and . IEEE Trans. Circuits Syst. Video Techn., 11 (11): 1149-1159 (2001)Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 376-387 (2020)Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology., , , and . ICECS, page 1217-1220. IEEE, (1999)Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination., , , and . ISCAS, page 3107-3110. IEEE, (2022)