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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

A. Grover, G. Visweswaran, C. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J. Noel, I. Panades, G. Moritz, E. Beigné, P. Flatresse, P. Kumar, and S. Azmi. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)

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Edith Krieghoff

Edith Wündisch

Edith Meinken

Edith Hartmann

Edith Arndt

Other publications of authors with the same name

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.B. Pelloux-Prayer, A. Valentian, B. Giraud, Y. Thonnart, J. Noel, P. Flatresse, and E. Beigné. VLSI-SoC, page 168-173. IEEE, (2013)Event-driven asynchronous voltage monitoring in energy harvesting platforms.J. Christmann, E. Beigné, C. Condemine, and C. Piguet. NEWCAS, page 457-460. IEEE, (2012)Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures.L. Vincent, E. Beigné, S. Lesecq, J. Mottin, D. Coriat, and P. Maurine. IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (6): 1741-1754 (2014)Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization.B. Rebaud, M. Belleville, E. Beigné, C. Bernard, M. Robert, P. Maurine, and N. Azémard. Microelectron. J., 42 (5): 718-732 (2011)Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee.D. Sylvester, K. Hirairi, and E. Beigné. ISSCC, page 298-299. IEEE, (2018)Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications.T. Wu, D. Kim, D. Morris, and E. Beigné. SiPS, page 1-3. IEEE, (2021)An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process.M. Ichihashi, H. Lhermet, E. Beigné, F. Rothan, M. Belleville, and A. Amara. PATMOS, volume 5953 of Lecture Notes in Computer Science, page 336-346. Springer, (2009)Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols.M. Maman, D. Morche, B. Martineau, C. Jany, I. Panades, A. Quelen, F. Badets, and E. Beigné. ICECS, page 789-792. IEEE, (2018)Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee.Y. Shin, P. Restle, and E. Beigné. ISSCC, page 116-117. IEEE, (2018)AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.D. Caucheteux, E. Beigné, E. Crochon, and M. Renaudin. ASYNC, page 86-97. IEEE Computer Society, (2006)

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Disambiguation of "Beigné, Edith"

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A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Please choose a person to relate this publication to

Edith Krieghoff

Edith Wündisch

Edith Meinken

Edith Hartmann

Edith Arndt

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Beigné, Edith"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.

Please choose a person to relate this publication to

Edith Krieghoff

Edith Wündisch

Edith Meinken

Edith Hartmann

Edith Arndt

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.