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FPGA acceleration in EVOLVE's Converged Cloud-HPC Infrastructure., , , , , , , , , and 1 other author(s). FPL, page 376-377. IEEE, (2021)VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1460-1464 (2019)Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing., , , , , and . FPL, page 74-80. IEEE, (2019)Optimizing SVM Classifier Through Approximate and High Level Synthesis Techniques., , , , and . MOCAST, page 1-4. IEEE, (2019)High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images., , , and . VLSI-SoC, page 1-6. IEEE, (2022)An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC., , , and . J. Signal Process. Syst., 88 (2): 127-147 (2017)FPGA Acceleration of Short Read Alignment., , and . HEART, page 13:1-13:2. ACM, (2021)Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach., , , , , , , and . DATE, page 622-625. IEEE, (2019)Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment., , and . DAC, page 1-6. IEEE, (2023)Exploration of GPU sharing policies under GEMM workloads., , , , and . SCOPES, page 66-69. ACM, (2020)