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Checking Reachability Properties for Timed Automata via SAT., , and . Fundam. Informaticae, 55 (2): 223-241 (2003)Bounded Model Checking for the Existential Fragment of TCTL-G and Diagonal Timed Automata., and . Fundam. Informaticae, 79 (1-2): 229-256 (2007)A Translator of Java Programs to TADDs., , and . Fundam. Informaticae, 93 (1-3): 305-324 (2009)Towards Bounded Model Checking for the Universal Fragment of TCTL., , and . FTRTFT, volume 2469 of Lecture Notes in Computer Science, page 265-290. Springer, (2002)Towards Verification of Java Programs in perICS., and . Fundam. Informaticae, 85 (1-4): 533-548 (2008)VerICS 2007 - a Model Checker for Knowledge and Real-Time., , , , , , , and . Fundam. Informaticae, 85 (1-4): 313-328 (2008)Verics: A Tool for Verifying Timed Automata and Estelle Specifications., , , , , , , and . TACAS, volume 2619 of Lecture Notes in Computer Science, page 278-283. Springer, (2003)Bounded Model Checking for the Universal Fragment of CTL., , and . Fundam. Informaticae, 51 (1-2): 135-156 (2002)ACTLS properties and Bounded Model Checking.. Fundam. Informaticae, 63 (1): 65-87 (2004)Bounded model checking for knowledge and real time., , and . AAMAS, page 165-172. ACM, (2005)