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Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study., , , and . DSD, page 390-397. IEEE Computer Society, (2009)Parallel Architecture Benchmarking: From Embedded Computing to HPC, a FiPS Project Perspective., , , , and . EUC, page 154-161. IEEE Computer Society, (2014)SESAM: An MPSoC Simulation Environment for Dynamic Application Processing., , , , , , and . CIT, page 1880-1886. IEEE Computer Society, (2010)A unified methodology for a fast benchmarking of parallel architecture., , and . DATE, page 1-4. European Design and Automation Association, (2014)SESAM/Par4All: a tool for joint exploration of MPSoC architectures and dynamic dataflow code generation., , , , and . RAPIDO, page 9-16. ACM, (2012)SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications., , , , , and . VLSI-SoC, page 341-346. IEEE, (2010)Hierarchical Network-on-Chip for Embedded Many-Core Architectures., , , and . NOCS, page 189-196. IEEE Computer Society, (2010)ARTM: a lightweight fork-join framework for many-core embedded systems., , , and . DATE, page 1510-1515. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Blockgraph proof-of-concept., , , , , , and . SIGCOMM Posters and Demos, page 82-84. ACM, (2021)PACHA: Low Cost Bare Metal Development for Shared Memory Manycore Accelerators., , , and . ICCS, volume 18 of Procedia Computer Science, page 1644-1653. Elsevier, (2013)