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Code Density and Energy Efficiency of Exposed Datapath Architectures., , , and . J. Signal Process. Syst., 80 (1): 49-64 (2015)ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA., , , , , and . J. Signal Process. Syst., 91 (1): 61-73 (2019)Variable Length Instruction Compression on Transport Triggered Architectures., , , , , , and . Int. J. Parallel Program., 46 (6): 1283-1303 (2018)Sparse Sampling for Real-time Ray Tracing, , , , , and . VISIGRAPP, (2018)Power optimizations for transport triggered SIMD processors., , , , , , , , , and 1 other author(s). SAMOS, page 303-309. IEEE, (2015)Variable length instruction compression on Transport Triggered Architectures., , , , , , and . ICSAMOS, page 149-155. IEEE, (2014)Design and implementation of a multi-mode harris corner detector architecture., , , , and . NORCAS, page 1-6. IEEE, (2017)Rapid customization of image processors using Halide., , , , and . GlobalSIP, page 629-633. IEEE, (2015)Exposed datapath optimizations for loop scheduling., , , , , , and . SAMOS, page 171-178. IEEE, (2017)Hardware design methodology using lightweight dataflow and its integration with low power techniques., , , , , , , , , and . J. Syst. Archit., (2017)