( en | de | ru )

 

Disambiguation of "Valero, Mateo"

Author of the publication

copydeleteadd this publication to your clipboard
An Abstraction Methodology for the Evaluation of Multi-core Multi-threaded Architectures.

, , , , , and . MASCOTS, page 478-481. IEEE Computer Society, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Alejandro Valero

Silvia Valero

 

Other publications of authors with the same name

Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications., , , , and . Euro-Par (1), volume 6852 of Lecture Notes in Computer Science, page 39-51. Springer, (2011)Overlapping communication and computation by using a hybrid MPI/SMPSs approach., , , and . ICS, page 5-16. ACM, (2010)The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Exploiting instruction- and data-level parallelism., and . IEEE Micro, 17 (5): 20-27 (1997)Multicore: The View from Europe., and . IEEE Micro, 30 (5): 2-4 (2010)Hardware Transactional Memory with Operating System Support, HTMOS., , , and . Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 8-17. Springer, (2007)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)