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Disambiguation of "Pal, Dipankar"

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ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder.

, , and . LASCAS, page 1-4. IEEE, (2020)

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Dipankar Mandal

Michael Pal

Andrea Pál

Pal Dragos

Aprameyo Pal

 

Other publications of authors with the same name

A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC., , , and . ISED, page 219-223. IEEE Computer Society, (2014)Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII., , , and . TENCON, page 7-10. IEEE, (2021)CCII+ based dual square-and-triangular waveform generator., and . ECAI, page 1-6. IEEE, (2017)A wide-input linear range sub-threshold transconductor for sub-Hz filtering., , and . ISCAS, page 1567-1570. IEEE, (2010)Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal Noise., and . Wireless Personal Communications, 100 (2): 505-518 (2018)Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier., and . ICICDT, page 29-32. IEEE, (2018)ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder., , and . LASCAS, page 1-4. IEEE, (2020)IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off., and . ICNC, page 626-629. IEEE, (2023)RF Harvesting System for Low-Power Applications Using FinFETs., , and . ICCE, page 1-6. IEEE, (2019)Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity., , , , and . IEEE Trans. Instrum. Meas., 58 (7): 2174-2180 (2009)