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Disambiguation of "Wu, An-Yeu"

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A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.

, , , , and . ISCAS (2), page 1074-1077. IEEE, (2005)

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Changseon Yeum

Danny Yeung

Thomas Yeung

Maureen W Yeung

Kam Yeung

 

Other publications of authors with the same name

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , and . ISCAS, page 869-872. IEEE, (2007)VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , and . ISCAS (2), page 773-776. IEEE, (2004)An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process., , , and . IEEE J. Solid State Circuits, 43 (3): 672-683 (2008)Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2485-2497 (2019)A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems., , and . EURASIP J. Adv. Signal Process., 2002 (9): 961-974 (2002)Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals., , , , and . CoRR, (2018)Compression-aware Projection with Greedy Dimension Reduction for Convolutional Neural Network Activations., , , and . CoRR, (2021)New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 532-536 (2013)Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (1): 119-136 (March 2023)Unsupervised Learning for Neural Network-based Polar Decoder via Syndrome Loss., and . CoRR, (2019)