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SERVAS! Secure Enclaves via RISC-V Authenticryption Shield.

, , , , and . ESORICS (2), volume 12973 of Lecture Notes in Computer Science, page 370-391. Springer, (2021)

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Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs., , , , and . IACR Cryptol. ePrint Arch., (2020)Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults., , , , , , , , and . IACR Cryptol. ePrint Arch., (2024)Exploiting Data-Usage Statistics for Website Fingerprinting Attacks on Android., , , and . WISEC, page 49-60. ACM, (2016)Side-Channel Plaintext-Recovery Attacks on Leakage-Resilient Encryption., , and . IACR Cryptology ePrint Archive, (2016)One for All - All for One: Unifying Standard DPA Attacks., , and . IACR Cryptology ePrint Archive, (2009)Exploiting the Difference of Side-Channel Leakages., , , , and . COSADE, volume 7275 of Lecture Notes in Computer Science, page 1-16. Springer, (2012)Protecting the Control Flow of Embedded Processors against Fault Attacks., , and . CARDIS, volume 9514 of Lecture Notes in Computer Science, page 161-176. Springer, (2015)Meltdown., , , , , , , , , and . CoRR, (2018)HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment., , , and . CoRR, (2020)Counteracting Power Analysis Attacks by Masking., and . Secure Integrated Circuits and Systems, Springer, (2010)