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A Coding Theoretic Approach towards Symmetrization in Reversible Circuit Synthesis., , and . J. Multiple Valued Log. Soft Comput., 35 (3-4): 239-262 (2020)Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection., , and . HPSR, page 164-170. IEEE, (2013)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey., , , and . SAMOS, page 167-172. ACM, (2018)New Speed Records for Salsa20 Stream Cipher Using an Autotuning Framework on GPUs., , and . AFRICACRYPT, volume 7918 of Lecture Notes in Computer Science, page 189-207. Springer, (2013)Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2469-2472 (2019)Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes., and . IEEE Trans. Computers, 65 (2): 640-653 (2016)Designing stream ciphers with scalable data-widths: a case study with HC-128., and . J. Cryptographic Engineering, 4 (2): 135-143 (2014)