( en | de | ru )

 

Disambiguation of "Torng, Christopher"

Author of the publication

copydeleteadd this publication to your clipboard
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.

, , , , , , , , , , , , , , , , , , , and . IEEE Micro, 38 (2): 30-41 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Christopher Christopher

Christopher Georgi

Christopher Künzel

Christopher Schumacher

Christopher Huth

 

Other publications of authors with the same name

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions., , and . IACR Cryptol. ePrint Arch., (2021)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays., , , , , and . IEEE Comput. Archit. Lett., 22 (1): 45-48 (January 2023)Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays., , , , , and . CoRR, (2022)Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration., , , , , , , , , and 13 other author(s). HCS, page 1-30. IEEE, (2022)Ultra-Elastic CGRAs for Irregular Loop Specialization., , , , and . HPCA, page 412-425. IEEE, (2021)Creating an Agile Hardware Design Flow., , , , , , , , , and 22 other author(s). DAC, page 1-6. IEEE, (2020)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)Enabling Reusable Physical Design Flows with Modular Flow Generators., , , , , , and . CoRR, (2021)Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays., , , , and . CoRR, (2023)