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Area compact 5T portless SRAM cell for high density cache in 65nm CMOS.

, , , and . VDAT, page 1-4. IEEE Computer Society, (2015)

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Non linear sparse recovery algorithm., , and . ISSPIT, page 327-332. IEEE Computer Society, (2014)Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling., , and . VLSID, page 591-592. IEEE Computer Society, (2016)Area compact 5T portless SRAM cell for high density cache in 65nm CMOS., , , and . VDAT, page 1-4. IEEE Computer Society, (2015)