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Disambiguation of "Tagliavini, Giuseppe"

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RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.

, , , , and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 16-32. Springer, (2021)

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Giuseppe Tagliavini

Giuseppe Olivato

Giuseppe Veltri

Giuseppe Amato

Giuseppe Valenza

 

Other publications of authors with the same name

Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 57 (1): 127-139 (2022)Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters., , , , , and . CoRR, (2023)Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers., , , , and . CoRR, (2020)Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms., , , , and . ICECS, page 1-8. IEEE, (2023)End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture., , , , , , and . DATE, page 1-6. IEEE, (2023)Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers., , , , and . DATE, page 878-883. IEEE, (2021)A transprecision floating-point cluster for efficient near-sensor data analytics., , , , , , , and . CoRR, (2020)Enabling Mixed-Precision Quantized Neural Networks in Extreme-Edge Devices., , , , and . CoRR, (2020)TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes., , , and . DATE, page 1-2. IEEE, (2023)4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode., , , , , , , , , and 2 other author(s). ISSCC, page 60-62. IEEE, (2021)