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Disambiguation of "Bui, Hung Tien"

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Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction.

, , , and . ISCAS, page 85-88. IEEE, (2011)

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Bui-Tien-Dung

Bui Tien Sy

Hung Tien Pham

Pei-Lin Tien

Hans Tienes

 

Other publications of authors with the same name

Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.. ISCAS, page 3422-3425. IEEE, (2008)Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction., , , and . ISCAS, page 85-88. IEEE, (2011)Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS)., , and . ISCAS, page 1312-1315. IEEE, (2010)Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector., and . ISCAS (4), page 369-372. IEEE, (2004)Dual-Path and Diode-Tracking Active Inductors for MCML Gates.. CCECE, page 1060-1063. IEEE, (2006)A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs., , , and . ISCAS, page 633-636. IEEE, (2007)Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop., and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (3): 766-774 (2008)10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS., and . IWSOC, page 115-118. IEEE Computer Society, (2004)Sensorless vector control of PMSG for variable speed wind energy applications., , , , and . CCECE, page 1-5. IEEE, (2010)Five new high-performance multiplexer-based 1-bit full adder cells., , and . ICECS, page 807-810. IEEE, (2001)