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Low-power multi-processor system architecture design for universal biomedical signal processing., , и . ISCAS, стр. 857-860. IEEE, (2013)CDSP: an application-specific digital signal processor for third generation wireless communications., , и . IEEE Trans. Consumer Electronics, 47 (3): 672-677 (2001)Reconfigurable architecture for video applications., , , , и . SoCC, стр. 21-24. IEEE, (2007)An efficient architecture for two-dimensional discrete wavelet transform., и . IEEE Trans. Circuits Syst. Video Techn., 11 (4): 536-545 (2001)Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000., , , и . IEEE Trans. Circuits Syst. Video Techn., 13 (3): 219-230 (2003)Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine., , , , , и . IEEE Trans. Circuits Syst. Video Techn., 18 (1): 98-109 (2008)A 212MPixels/s 4096×2160p multiview video encoder chip for 3D/quad HDTV applications., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 154-155. IEEE, (2009)A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm., и . IEEE Trans. Circuits Syst. Video Techn., 8 (2): 124-127 (1998)Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform., , и . APCCAS (1), стр. 383-388. IEEE, (2002)A 100 MHz 1920×1080 HD-Photo 20 frames/sec JPEG XR encoder design., , , , , , , , , и . ICIP, стр. 1384-1387. IEEE, (2008)