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EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , and . FPGA, page 142-151. ACM, (2019)GSA to HDL: Towards principled generation of dynamically scheduled circuits., , , and . CoRR, (2023)SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR., , , , and . CoRR, (2023)Probabilistic Optimization for High-Level Synthesis., , and . FPGA, page 145. ACM, (2021)Building a comprehensive syntactic and semantic corpus of Chinese clinical texts., , , , , , , and . CoRR, (2016)Probabilistic Scheduling in High-Level Synthesis., , and . FCCM, page 195-203. IEEE, (2021)Combining Dynamic & Static Scheduling in High-level Synthesis., , , , and . FPGA, page 288-298. ACM, (2020)DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 628-641 (2022)ScaleHLS: Scalable High-Level Synthesis through MLIR., , , , , , and . CoRR, (2021)ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation., , , , , , and . HPCA, page 741-755. IEEE, (2022)