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Data Leakage via Access Patterns of Sparse Features in Deep Learning-based Recommendation Systems.

, , , , , , and . CoRR, (2022)

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Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (1): 1-13 (2013)Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (1): 38-52 (2007)Adaptive transaction scheduling for transactional memory systems., and . SPAA, page 169-178. ACM, (2008)Kicking the tires of software transactional memory: why the going gets tough., , , , , and . SPAA, page 265-274. ACM, (2008)An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems., , and . FPL, page 47-53. IEEE, (2007)Region-based caching: an energy-delay efficient memory architecture for embedded processors., and . CASES, page 120-127. ACM, (2000)SimWare: A Holistic Warehouse-Scale Computer Simulator., and . Computer, 45 (9): 48-55 (2012)Chasing Carbon: The Elusive Environmental Footprint of Computing., , , , , , , and . IEEE Micro, 42 (4): 37-47 (2022)Energy-Efficient Network Memory for Ubiquitous Devices., , , , and . IEEE Micro, 23 (5): 60-70 (2003)Profile-guided microarchitectural floor planning for deep submicron processor design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (7): 1289-1300 (2006)