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Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.

, and . IEEE Trans. Computers, 40 (1): 66-79 (1991)

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A backtracing-oriented procedure for the analysis of combinational gate-level designs., and . Integr., 17 (3): 271-286 (1994)RIDDLE: A Foundation for Test Generation on a High-Level Design Description., and . IEEE Trans. Computers, 40 (1): 80-87 (1991)Linear test sequences for detecting functionally faulty RAM's., , and . Integr., 16 (1): 75-89 (1993)Retiming revisited and reversed., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (3): 348-357 (1996)The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage., and . ITC, page 332-339. IEEE Computer Society, (1986)Guest Editors' Introduction., and . J. Instruction-Level Parallelism, (2000)G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing., and . ITC, page 764-772. IEEE Computer Society, (1988)Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers., and . ISCA, page 106-113. ACM, (1992)Whistle: A Workbench for Test Development of Library-Based Designs., , and . Computer, 22 (4): 27-41 (1989)Using functional fault simulation and the difference fault model to estimate implementation fault coverage., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (12): 1335-1343 (1990)