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Disambiguation of "Janssen, Erwin"

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15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS.

, , , and . ISSCC, page 1-3. IEEE, (2015)

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Thomas Erwin

Günther Erwin

Erwinsyah

Elena Erwin

Claudia Erwin

 

Other publications of authors with the same name

A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 116-120 (2017)Description of limit cycles in sigma-delta modulators., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (6): 1211-1223 (2005)A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS., , , , and . IEEE J. Solid State Circuits, 46 (12): 2821-2833 (2011)An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS., , , , , , , , and . ISSCC, page 464-465. IEEE, (2013)15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS., , , and . ISSCC, page 1-3. IEEE, (2015)Super-audio CD: an introduction., and . IEEE Signal Process. Mag., 20 (4): 83-90 (2003)A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS., , , and . IEEE J. Solid State Circuits, 50 (12): 2891-2900 (2015)Lossless compression of one-bit audio., , , and . ICASSP (3), page 1020-1023. IEEE, (2004)A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist., , , , and . ISSCC, page 180-182. IEEE, (2011)An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals., , , , , , , and . ESSCIRC, page 121-124. IEEE, (2013)