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Disambiguation of "Milder, Peter A."

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A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAs.

, , , , and . FPGA, page 87-96. ACM, (2018)

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Peter A Ehrl

Peter A Schmid

Peter A Wuffli

Peter A Ehrl

Peter A Gloor

 

Other publications of authors with the same name

Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only)., , , and . FPGA, page 271. ACM, (2012)Waverunner: An Elegant Approach to Hardware Acceleration of State Machine Replication., , , , , and . NSDI, page 357-374. USENIX Association, (2023)Argus: An End-to-End Framework for Accelerating CNNs on FPGAs., , , and . IEEE Micro, 39 (5): 17-25 (2019)Error Probability Models for Voltage-Scaled Multiply-Accumulate Units., , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (7): 1665-1675 (2020)FPGA-Accelerated Samplesort for Large Data Sets., , , and . FPGA, page 222-232. ACM, (2020)Pub/Sub in the Air: A Novel Data-centric Radio Supporting Robust Multicast in Edge Environments., , , and . SEC, page 257-270. IEEE, (2020)Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only)., , and . FPGA, page 293. ACM, (2017)Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes., , , and . FCCM, page 188-191. IEEE Computer Society, (2012)MEMOCODE 2015 design contest: Continuous skyline computation.. MEMOCODE, page 48-51. IEEE, (2015)Guest Editorial: IEEE TC Special Issue: Hardware Acceleration of Machine Learning., , , and . IEEE Trans. Computers, 71 (12): 3072-3073 (2022)