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A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.

, , , and . IEEE J. Solid State Circuits, 54 (4): 1152-1160 (2019)

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A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell., , , and . IEEE J. Solid State Circuits, 54 (4): 1152-1160 (2019)A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (2): 557-567 (2016)Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics., , , and . A-SSCC, page 177-180. IEEE, (2016)An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access., and . ISSCC, page 318-319. IEEE, (2013)A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS., , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 188-198 (2021)A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 231-239 (2019)Challenges and Directions for Low-Voltage SRAM., , and . IEEE Des. Test Comput., 28 (1): 32-43 (2011)A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS., , and . IEEE J. Solid State Circuits, 44 (11): 3163-3173 (2009)Low-power and application-specific SRAM design for energy-efficient motion estimation.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2012)ndltd.org (oai:dspace.mit.edu:1721.1/75650).A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz., , and . ESSCIRC, page 282-285. IEEE, (2008)