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A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution., , и . ESSCIRC, стр. 155-158. IEEE, (2011)Block-based multiperiod dynamic memory design for low data-retention power., и . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 1006-1018 (2003)Design of a 20-mb/s 256-state Viterbi decoder., и . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 965-975 (2003)Retiming edge-triggered circuits under general delay models., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (12): 1393-1408 (1997)Practical repeater insertion for low power: what repeater library do we need?, , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (5): 917-924 (2006)Resonant-Clock Latch-Based Design., , и . IEEE J. Solid State Circuits, 43 (4): 864-873 (2008)Incorporation of input glitches into power macromodeling., и . ISCAS (4), стр. 846-849. IEEE, (2002)Maximizing Performance by Retiming and Clock Skew Scheduling., , и . DAC, стр. 231-236. ACM Press, (1999)A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead., , , и . ESSCIRC, стр. 160-163. IEEE, (2009)HyPE: hybrid power estimation for IP-based programmable systems., и . ASP-DAC, стр. 606-609. ACM, (2003)