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Disambiguation of "Navabi, Zainalabedin"

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Utilizing Various ADL Facets for Instruction Level CPU Test.

, , , and . MTV, page 38-. IEEE Computer Society, (2003)

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Kambiz Navabi

Foroogh Navabi-Kermani

 

Other publications of authors with the same name

Near-Optimal Node Selection Procedure for Aging Monitor Placement., , and . IOLTS, page 6-11. IEEE, (2018)SCOAP-based Directed Random Test Generation for Combinational Circuits., , , and . EWDTS, page 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements., , , , , , and . EWDTS, page 1-6. IEEE, (2019)An off-line MDSI interconnect BIST incorporated in BS 1149.1., , , and . ETS, page 1-2. IEEE, (2014)On-Chip Verification of NoCs Using Assertion Processors., , , , and . DSD, page 535-538. IEEE Computer Society, (2007)Back-annotation of gate-level power properties into system level descriptions., and . NEWCAS, page 237-240. IEEE, (2014)A high-level language for design and modeling of hardware.. J. Syst. Softw., 18 (1): 5-18 (1992)A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies., , , , , and . Integr., (2015)Structure Specification with a Procedural Hardware Description Language., , , and . IEEE Trans. Computers, 30 (2): 157-161 (1981)A Selective Trigger Scan Architecture for VLSI Testing., , , and . IEEE Trans. Computers, 57 (3): 316-328 (2008)