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A synthesizable time-based LDO using digital standard cells and analog pass transistor., , , , , и . ESSCIRC, стр. 271-274. IEEE, (2017)Low-power design methodology for an on-chip bus with adaptive bandwidth capability., , и . DAC, стр. 628-633. ACM, (2003)A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring., и . IEEE J. Solid State Circuits, 51 (2): 473-483 (2016)An optimal design methodology for inductive power link with class-E amplifier., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (5): 857-866 (2005)A 0.45V CMOS relaxation oscillator with ±2.5% frequency stability from -55°C to 125°C., , и . ISCAS, стр. 493-496. IEEE, (2015)A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring., и . VLSIC, стр. 1-2. IEEE, (2014)A 12.4-mW 4.5-Gb/s Receiver With Majority-Voting 1-Tap Speculative DFE in 0.13- µm CMOS., и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (12): 867-871 (2013)Simplified delay design guidelines for on-chip global interconnects., , , , и . ACM Great Lakes Symposium on VLSI, стр. 29-32. ACM, (2004)Delay and power model for current-mode signaling in deep submicron global interconnects., , и . CICC, стр. 513-516. IEEE, (2002)A 90-240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking., , , и . CICC, стр. 21-24. IEEE, (2008)