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A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

, , , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)

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Yoichi Kiuchi

Yoichi Otani

Yoichi Ishikawa

 

Другие публикации лиц с тем же именем

Fault Tolerant Neural Networks in Optimization Problems., и . FTCS, стр. 412-418. IEEE Computer Society, (1992)Design of Neural Networks to Tolerate the Mixture of Two Types of Faults., и . FTCS, стр. 268-277. IEEE Computer Society, (1993)Fault-Tolerant Design of Neural Networks for Solving Optimization Problems., и . IEEE Trans. Computers, 45 (12): 1450-1455 (1996)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 64-65. IEEE, (2016)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , и . VLSIC, стр. 1-2. IEEE, (2014)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 36-37. IEEE, (2013)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , и . ISSCC, стр. 40-41. IEEE, (2013)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (12): 3258-3267 (2013)A 10th generation 16-core SPARC64 processor for mission-critical UNIX server., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 60-61. IEEE, (2013)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , и . ISSCC, стр. 346-348. IEEE, (2011)