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ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator., , , , , , , , , and . IEEE Micro, 42 (6): 76-87 (2022)Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (3): 1650-1655 (March 2024)Gradient descent-based programming of analog in-memory computing cores., , , , , , , , , and 4 other author(s). CoRR, (2023)Energy Efficient In-memory Hyperdimensional Encoding for Spatio-temporal Signal Processing., , , , , , and . CoRR, (2021)Accurate Weight Mapping in a Multi-Memristive Synaptic Unit., , , , , , , , , and . ISCAS, page 1-5. IEEE, (2021)Mixed-precision architecture based on computational memory for training deep neural networks., , , , , and . ISCAS, page 1-5. IEEE, (2018)Robust High-dimensional Memory-augmented Neural Networks., , , , , , and . CoRR, (2020)HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 57 (4): 1027-1038 (2022)A Multi-Memristive Unit-Cell Array With Diagonal Interconnects for In-Memory Computing., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (12): 3522-3526 (2021)Temporal correlation detection using computational phase-change memory., , , , , , and . CoRR, (2017)