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1ZuSE KI-AVF
G. Thieu, S. Gesper, G. Payá-Vayá, C. Riggers, O. Renke, T. Fiedler, J. Marten, T. Stuckenberg, H. Blume, C. Weis and 18 other author(s). (2023)
9 months ago by @fabcho
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myown
FPGA
AI
vertical
processor
acceleration
system
ASIC
RISC-V
processing
hardware-software
sensor
vector
myownFPGAAIverticalprocessoraccelerationsystemASICRISC-Vprocessinghardware-softwaresensorvector
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1Study of FPGA Based Multi Channel Analyzer for Gamma Ray and X Ray Spectrometry
M. Akhter. International Journal of Trend in Scientific Research and Development, 3 (3): 61-65 (April 2019)
6 years ago by @ijtsrd
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Engineering
Multi-channel
Detector
FPGA
Device
Pulse
Nuclear
Height
Processing
Analyzer
EngineeringMulti-channelDetectorFPGADevicePulseNuclearHeightProcessingAnalyzer
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2A Highly Parallel FPGA Implementation of Sparse Neural Network Training
S. Dey, D. Chen, Z. Li, S. Kundu, K. Huang, K. Chugg, and P. Beerel. 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), page 1--4. IEEE, (2018)
6 years ago by @loroch
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hardware
FPGA
training
deep_learning
embedded
architecture
hardwareFPGAtrainingdeep_learningembeddedarchitecture
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1Field-programmable logic and application : reconfigurable computing is going mainstream : 12th international conference, FPL 2002, Montpellier, France, September 2-4, 2002 : proceedings
I. on Field-Programmable Logic, Applications, M. Glesner, P. Zipf, and M. Renovell. Springer, (2002)
6 years ago by @karthikraman
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evolvable-hardware
fpga
evolvable-hardwarefpga
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1Design and Implementation of Lifting Based Wavelet and Adaptive LSB Steganography to Secret Data Sharing Through Image on FPGA
K. Padeppagol, and S. H. International Journal of Engineering and Management Research, 8 (3): 112-119 (2018)
6 years ago by @amarjeetsingh
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DWT
Steganography
FPGA
Artix7
and
Encryption
LSB
Decryption
Image
DWTSteganographyFPGAArtix7andEncryptionLSBDecryptionImage
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1COMPARISON OF CHANNEL ESTIMATION AND EQUALIZATION TECHNIQUES FOR OFDM SYSTEMS
S. T, and S. N. Circuits and Systems: An International Journal (CSIJ), 1 (1): 1-10 (January 2014)
7 years ago by @csijjournal1821
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fpga
attacks
cognitive
k-type
gaussian
fpgaattackscognitivek-typegaussian
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2Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL
H. Waidyasooriya, M. Hariyama, and K. Kasahara. 2016 IEEE/ACIS 15th International Conference on Computer and Information Science (ICIS), page 1-5. (June 2016)
7 years ago by @salotz
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hardware
opencl
molecular-dynamics
fpga
software
hardwareopenclmolecular-dynamicsfpgasoftware
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1Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
C. Baskin, N. Liss, E. Zheltonozhskii, A. Bronshtein, and A. Mendelson. (2017)cite arxiv:1708.00052Comment: Will appear in RAW 2018.
7 years ago by @jk_itwm
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FPGA
FPGA
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1FNOCEE: A framework for NoC evaluation by FPGA-based emulation
D. Pfefferkorn, A. Schmider, G. Payá-Vayá, M. Neuenhahn, and H. Blume. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, page 86-95. (July 2015)
9 years ago by @imsl3s
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NoC
myown
FPGA
2015
NoCmyownFPGA2015
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1Realtime FPGA-based processing unit for a high-resolution automotive MIMO radar platform
F. Meinl, E. Schubert, M. Kunert, and H. Blume. Radar Conference (EuRAD), 2015 European, page 213-216. (September 2015)
9 years ago by @imsl3s
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myown
fpga
2015
MIMO
myownfpga2015MIMO
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1To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques
R. Rewatkar, and D. Badjate. International Journal on Recent and Innovation Trends in Computing and Communication, 3 (3): 1562--1571 (March 2015)
9 years ago by @ijritcc
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Finite
large
FIR
DSP-Digital
response
gate
impulse
MCM-Multiple
Multiplication
Constant
FPGA
circuit
VHDL-Very
language
VLSI-Very
scale
description
Processing
Programmable
integrated
speed
hardware
high
Field
array
Signal
FinitelargeFIRDSP-DigitalresponsegateimpulseMCM-MultipleMultiplicationConstantFPGAcircuitVHDL-VerylanguageVLSI-VeryscaledescriptionProcessingProgrammableintegratedspeedhardwarehighFieldarraySignal
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1A Review on Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics
S. Salim, and S. Lakhotiya. International Journal on Recent and Innovation Trends in Computing and Communication, 3 (1): 162--164 (January 2015)
9 years ago by @ijritcc
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exponentiation
Multiplication
VHDL
FPGA
Vedic
Modular
Mathematics
Cryptosystem
RSA
exponentiationMultiplicationVHDLFPGAVedicModularMathematicsCryptosystemRSA
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2A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services
A. Putnam, A. Caulfield, E. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. Gopal, J. Gray and 13 other author(s). Proceeding of the 41st Annual International Symposium on Computer Architecuture, page 13--24. Piscataway, NJ, USA, IEEE Press, (2014)
9 years ago by @csl_uth
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FPGA
FPGA
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1Development of Soft-Core Processor System on FPGA
A. Kamaraju, B. Parveen, and and C. T. Jaya Prakash. (2014)
11 years ago by @idescitation
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tool
system
FPGA
SOPC
EDK
Micro-BlazeSoft-core
processor
toolsystemFPGASOPCEDKMicro-BlazeSoft-coreprocessor
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3Fisheye lens distortion correction on multicore and hardware accelerator platforms
K. Daloukas, C. Antonopoulos, N. Bellas, and S. Chai. IPDPS, page 1-10. (2010)
12 years ago by @csl_uth
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multicore
FPGA
GPU
cda
multicoreFPGAGPUcda
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1Development of embedded PC and FPGA based systems with virtual hardware
W. Zabolotny. Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2012, 8454, page 84540S. SPIE, (2012)
12 years ago by @wzab
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based
hardware
pc
development
virtual
fpga
embedded
basedhardwarepcdevelopmentvirtualfpgaembedded
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1Studying the Optimal Parameter Range of Values in PADGP by Means of Real-life Problems
F. Fernandez, and M. Tomassini. Proceedings of the 2001 Congress on Evolutionary Computation CEC2001, page 436--441. COEX, World Trade Center, 159 Samseong-dong, Gangnam-gu, Seoul, Korea, IEEE Press, (27-30 May 2001)
17 years ago by @brazovayeye
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genetic
Programming,
FPGA
algorithms,
programming,
Genetic
Parallel
geneticProgramming,FPGAalgorithms,programming,GeneticParallel
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2The FPGA High-Performance Computing Alliance Parallel Toolkit
R. Baxter, S. Booth, M. Bull, G. Cawood, J. Perry, M. Parsons, A. Simpson, A. Trew, A. McCormick, G. Smart and 4 other author(s). Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on, page 301-310. (2007)
17 years ago by @ykwok
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fpga
PETSc
fpgaPETSc
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publications (hide)18
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