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1Accelerating Attention Mechanism on FPGAs based on efficient Reconfigurable Systolic Array
wenhua ye. (2023)
2 years ago by @csl_uth
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FPGA
ML
FPGAML
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1Feature Pyramid Networks for Object Detection
T. Lin, P. Dollár, R. Girshick, K. He, B. Hariharan, and S. Belongie. CoRR, (2016)
2 years ago by @csl_uth
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FPGA
ML
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2FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization
M. Sun, Z. Li, A. Lu, Y. Li, S. Chang, X. Ma, X. Lin, and Z. Fang. FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022, page 134--145. ACM, (2022)
2 years ago by @csl_uth
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FPGA
ML
Quantization
FPGAMLQuantization
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2HAQ: Hardware-Aware Automated Quantization With Mixed Precision.
K. Wang, Z. Liu, Y. Lin, J. Lin, and S. Han. CVPR, page 8612-8620. Computer Vision Foundation / IEEE, (2019)
2 years ago by @csl_uth
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FPGA
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Quantization
FPGAMLQuantization
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2MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM
Y. Liu, J. Li, K. Huang, X. Li, X. Qi, L. Chang, Y. Long, and J. Zhou. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (12): 4919--4929 (2022)
2 years ago by @csl_uth
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FPGA
ML
SLAM
FPGAMLSLAM
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2Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems
K. Manev, A. Vaishnav, and D. Koch. 2019 International Conference on Field-Programmable Technology (ICFPT), page 179-187. (2019)
3 years ago by @csl_uth
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FPGA
FPGA
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1A Survey of FPGA-Based Robotic Computing.
Z. Wan, B. Yu, T. Li, J. Tang, Y. Zhu, Y. Wang, A. Raychowdhury, and S. Liu. CoRR, (2020)
3 years ago by @csl_uth
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FPGA
SLAM
FPGASLAM
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2A CAD-based methodology to optimize HLS code via the Roofline model
M. Siracusa, M. Rabozzi, E. Sozzo, L. Tucci, S. Williams, and M. Santambrogio. IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, page 116:1--116:9. IEEE, (2020)
3 years ago by @csl_uth
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Roofline
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1Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.
K. Yamashina, T. Ohkawa, K. Ootsu, and T. Yokota. CoRR, (2015)
4 years ago by @csl_uth
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ROS
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FPGAROSSLAM
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2A Methodology for Principled Approximation in Visual SLAM.
Y. Pei, S. Biswas, D. Fussell, and K. Pingali. PACT, page 373-386. ACM, (2020)
4 years ago by @csl_uth
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1Embedding SLAM algorithms: Has it come of age?
M. Abouzahir, A. Elouardi, R. Latif, S. Bouaziz, and A. Tajer. Robotics and Autonomous Systems, (2018)
5 years ago by @csl_uth
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SLAM
FPGASLAM
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2Real-time large-scale dense RGB-D SLAM with volumetric fusion
T. Whelan, M. Kaess, H. Johannsson, M. Fallon, J. Leonard, and J. McDonald. International Journal of Robotics Research, 34 (4-5): 598--626 (2015)
5 years ago by @csl_uth
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SLAM
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2A Scalable FPGA-Based Architecture for Depth Estimation in SLAM
K. Boikos, and C. Bouganis. Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings, page 181--196. (2019)
5 years ago by @csl_uth
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2A high-performance system-on-chip architecture for direct tracking for SLAM.
K. Boikos, and C. Bouganis. FPL, page 1-7. IEEE, (2017)
5 years ago by @csl_uth
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SLAM
FPGASLAM
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2Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories
B. Salami, O. Unsal, and A. Kestelman. 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018, page 724--736. (2018)
6 years ago by @csl_uth
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reliability
FPGAreliability
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2An FPGA-based real-time simultaneous localization and mapping system.
M. Gu, K. Guo, W. Wang, Y. Wang, and H. Yang. FPT, page 200-203. IEEE, (2015)
6 years ago by @csl_uth
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SLAM
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2FPGA-based ORB Feature Extraction for Real-Time Visual SLAM.
W. Fang, Y. Zhang, B. Yu, and S. Liu. CoRR, (2017)
6 years ago by @csl_uth
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SLAM
FPGASLAM
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2Plasticine: A Reconfigurable Architecture For Parallel Paterns
R. Prabhakar, Y. Zhang, D. Koeplinger, M. Feldman, T. Zhao, S. Hadjis, A. Pedram, C. Kozyrakis, and K. Olukotun. Proceedings of the 44th Annual International Symposium on Computer Architecture, page 389--402. New York, NY, USA, ACM, (2017)
6 years ago by @csl_uth
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synthesis
FPGAsynthesis
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2An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures
J. Korinth, D. de la Chevallerie, and A. Koch. 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015, page 195--198. (2015)
8 years ago by @csl_uth
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FPGA
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2Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions
M. Belwal, M. Purnaprajna, and T. Sudarshan. 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, page 1--8. (2015)
8 years ago by @csl_uth
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BibSonomy

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publications (hide)36
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1Accelerating Attention Mechanism on FPGAs based on efficient Reconfigurable Systolic Array

1Feature Pyramid Networks for Object Detection

2FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization

2HAQ: Hardware-Aware Automated Quantization With Mixed Precision.

2MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM

2Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems

1A Survey of FPGA-Based Robotic Computing.

2A CAD-based methodology to optimize HLS code via the Roofline model

1Proposal of ROS-compliant FPGA Component for Low-Power Robotic Systems.

2A Methodology for Principled Approximation in Visual SLAM.

1Embedding SLAM algorithms: Has it come of age?

2Real-time large-scale dense RGB-D SLAM with volumetric fusion

2A Scalable FPGA-Based Architecture for Depth Estimation in SLAM

2A high-performance system-on-chip architecture for direct tracking for SLAM.

2Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

2An FPGA-based real-time simultaneous localization and mapping system.

2FPGA-based ORB Feature Extraction for Real-Time Visual SLAM.

2Plasticine: A Reconfigurable Architecture For Parallel Paterns

2An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures

2Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions

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