%0 Journal Article %1 journals/tcad/GongWLCZ18 %A Gong, Lei %A Wang, Chao %A Li, Xi %A Chen, Huaping %A Zhou, Xuehai %D 2018 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K %N 11 %P 2601-2612 %T MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip. %U http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#GongWLCZ18 %V 37

@article{journals/tcad/GongWLCZ18, added-at = {2023-12-12T17:34:16.000+0100}, author = {Gong, Lei and Wang, Chao and Li, Xi and Chen, Huaping and Zhou, Xuehai}, biburl = {https://www.bibsonomy.org/bibtex/2e9b51bc815b161985db3ba6e9a727073/admin}, ee = {https://doi.org/10.1109/TCAD.2018.2857078}, interhash = {059cfa83d12798113603eda2cd846f6d}, intrahash = {e9b51bc815b161985db3ba6e9a727073}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {}, number = 11, pages = {2601-2612}, timestamp = {2023-12-12T17:34:16.000+0100}, title = {MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#GongWLCZ18}, volume = 37, year = 2018 }