Inproceedings,
Capture power reduction using clock gating aware test generation.
K. Chakravadhanula, V. Chickermane, B. Keller, P. Jr., and P. Narang.ITC, page 1-9. IEEE Computer Society, (2009)
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- conf/itc/ChakravadhanulaCKGN09
- entry type
- inproceedings
- booktitle
- ITC
- year
- 2009
- pages
- 1-9
- publisher
- IEEE Computer Society
- crossref
- conf/itc/2009
- ee
- https://doi.ieeecomputersociety.org/10.1109/TEST.2009.5355649
- isbn
- 978-1-4244-4868-5
- url
- http://dblp.uni-trier.de/db/conf/itc/itc2009.html#ChakravadhanulaCKGN09
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%1 conf/itc/ChakravadhanulaCKGN09
%A Chakravadhanula, Krishna
%A Chickermane, Vivek
%A Keller, Brion L.
%A Jr., Patrick R. Gallagher
%A Narang, Prashant
%B ITC
%D 2009
%E Roberts, Gordon W.
%E Eklow, Bill
%I IEEE Computer Society
%K dblp
%P 1-9
%T Capture power reduction using clock gating aware test generation.
%U http://dblp.uni-trier.de/db/conf/itc/itc2009.html#ChakravadhanulaCKGN09
%@ 978-1-4244-4868-5
@inproceedings{conf/itc/ChakravadhanulaCKGN09,
added-at = {2023-03-23T00:00:00.000+0100},
author = {Chakravadhanula, Krishna and Chickermane, Vivek and Keller, Brion L. and Jr., Patrick R. Gallagher and Narang, Prashant},
biburl = {https://www.bibsonomy.org/bibtex/20ca4c9630550d041e0f4ffe4dbdd6191/dblp},
booktitle = {ITC},
crossref = {conf/itc/2009},
editor = {Roberts, Gordon W. and Eklow, Bill},
ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.2009.5355649},
interhash = {06903b4e6d112b20dc2114d1da83e94f},
intrahash = {0ca4c9630550d041e0f4ffe4dbdd6191},
isbn = {978-1-4244-4868-5},
keywords = {dblp},
pages = {1-9},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T04:29:19.000+0200},
title = {Capture power reduction using clock gating aware test generation.},
url = {http://dblp.uni-trier.de/db/conf/itc/itc2009.html#ChakravadhanulaCKGN09},
year = 2009
}