%0 Journal Article %1 journals/ijnc/HirayamaAMT20 %A Hirayama, Yuki %A Asai, Tetsuya %A Motomura, Masato %A Takamaeda, Shinya %D 2020 %J Int. J. Netw. Comput. %K dblp %N 2 %P 84-93 %T A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. %U http://dblp.uni-trier.de/db/journals/ijnc/ijnc10.html#HirayamaAMT20 %V 10

@article{journals/ijnc/HirayamaAMT20, added-at = {2021-02-16T00:00:00.000+0100}, author = {Hirayama, Yuki and Asai, Tetsuya and Motomura, Masato and Takamaeda, Shinya}, biburl = {https://www.bibsonomy.org/bibtex/29b8abae4b514d709811d12f5049546de/dblp}, ee = {http://www.ijnc.org/index.php/ijnc/article/view/222}, interhash = {116055818825288899cd332b884016e4}, intrahash = {9b8abae4b514d709811d12f5049546de}, journal = {Int. J. Netw. Comput.}, keywords = {dblp}, number = 2, pages = {84-93}, timestamp = {2024-04-08T20:13:53.000+0200}, title = {A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks.}, url = {http://dblp.uni-trier.de/db/journals/ijnc/ijnc10.html#HirayamaAMT20}, volume = 10, year = 2020 }