%0 Journal Article %1 journals/sigarch/ZhaoIUN08 %A Zhao, Li %A Iyer, Ravi R. %A Upton, Mike %A Newell, Don %D 2008 %J SIGARCH Comput. Archit. News %K dblp %N 2 %P 56-63 %T Towards hybrid last level caches for chip-multiprocessors. %U http://dblp.uni-trier.de/db/journals/sigarch/sigarch36.html#ZhaoIUN08 %V 36

@article{journals/sigarch/ZhaoIUN08, added-at = {2023-05-15T00:00:00.000+0200}, author = {Zhao, Li and Iyer, Ravi R. and Upton, Mike and Newell, Don}, biburl = {https://www.bibsonomy.org/bibtex/2b6735a9a72dfd4e89325452418cf1624/dblp}, ee = {https://doi.org/10.1145/1399972.1399982}, interhash = {1a464e6301fa36e4d1e33b4bd34e2e10}, intrahash = {b6735a9a72dfd4e89325452418cf1624}, journal = {SIGARCH Comput. Archit. News}, keywords = {dblp}, number = 2, pages = {56-63}, timestamp = {2024-04-08T09:55:53.000+0200}, title = {Towards hybrid last level caches for chip-multiprocessors.}, url = {http://dblp.uni-trier.de/db/journals/sigarch/sigarch36.html#ZhaoIUN08}, volume = 36, year = 2008 }