%0 Journal Article %1 journals/jssc/HsiehKH18 %A Hsieh, Sung-En %A Kao, Chen-Che %A Hsieh, Chih-Cheng %D 2018 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2763-2771 %T A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization. %U http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#HsiehKH18 %V 53

@article{journals/jssc/HsiehKH18, added-at = {2020-08-30T00:00:00.000+0200}, author = {Hsieh, Sung-En and Kao, Chen-Che and Hsieh, Chih-Cheng}, biburl = {https://www.bibsonomy.org/bibtex/267a07eb88f4d460f8b4665ca4e2ee5bd/dblp}, ee = {https://doi.org/10.1109/JSSC.2018.2862880}, interhash = {2467fe4284df0f8903d3a93cef5f9615}, intrahash = {67a07eb88f4d460f8b4665ca4e2ee5bd}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2763-2771}, timestamp = {2020-08-31T11:42:10.000+0200}, title = {A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc53.html#HsiehKH18}, volume = 53, year = 2018 }