Author of the publication

A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization.

, , and . IEEE J. Solid State Circuits, 53 (10): 2763-2771 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 59 (1): 219-230 (January 2024)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction., , , , , , and . IEEE J. Solid State Circuits, 56 (5): 1588-1596 (2021)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (5): 1550-1562 (2022)A signal acquisition and processing chip with built-in cluster for chemiresistive gas sensor array., , , , , , , , and . NEWCAS, page 428-431. IEEE, (2014)Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor., , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)Live demonstration: The prototype of real-time image pre-processing system for satellites' remote sensing., , , , , , , , and . ISCAS, page 1992-1996. IEEE, (2011)A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS., and . A-SSCC, page 157-160. IEEE, (2016)A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS., and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (1): 70-79 (2015)